An embodiment of the invention is directed to an integrated circuit having an information storage cell array, and techniques for reading a cell of the array in a manner that increases a difference in signal voltages from the cell. Other embodiments are also described.
Microelectronic information storage arrays, such as those used in caches and memories, have been expanding in capacity and size to accommodate greater information storage needs. This has led to the development of storage arrays that are denser, that is, have a greater number of cells per unit area of an integrated circuit die. For example, in the field of dynamic random access memories (DRAMs), an array that includes single-transistor gain cells (that amplify a small storage charge) has been proposed. A problem with such an array is that its gain cell, which is made of one or more metal oxide semiconductor (MOS) field effect transistor (FET) devices, exhibits relatively significant leakage from the gate structure of the FET device at a storage node of the cell. As the dimensions of the cell and its constituent transistors decrease, the time interval over which the state of the cell can be retained and read out, without requiring a “refresh”, is reduced, due to this leakage. Refresh refers to the periodic referencing of the storage cells in the array, which typically recharges the data-storage nodes of the cell in order to maintain data integrity.
Data integrity may also be improved by adding a “discrete” or non-parasitic capacitor structure to the storage node. This helps reduce the required refresh rate for the array, however, it does make the gain cell larger and therefore reduces the array density. A two-transistor gain cell has been proposed with such a discrete capacitor on the storage node. N. Ikeda, et al. “A Novel Logic Compatible Gain Cell With Two Transistors and One Capacitor”, (2000 Symposium on VLSI Technology, pages 168-169, June 2000).